Che-Kai Liu
Ph.D. Student @ GaTech ECE
Email: che-kai@gatech.edu
Focus: Mixed-signal VLSI and Computer Architecture.
About Me
Hello, I am a 1st year Ph.D. student advised by Professor Arijit Raychowdhury at the Integrated Circuits and Systems Research Lab, School of Electrical and Computer Engineering, Georgia Institute of Technology. I am also fortunate to gain chip design insights from Professor Visvesh S. Sathe. My current research focus is on analog/digital/mix-signal physical chip and architecture design for next-generation AI workloads. Before joining the Tech, my research was compute-in-memroy (CIM) hardware-algorithm co-design in electronic design automation (EDA) [ICCAD22,23][DATE23,24b].
Peer-reviewed Publications. *Equal Contributions
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Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI
Z. Wan, C.-K. Liu, H. Yang, R. Raj, C. Li, H. You, Y. Fu, C. Wan, A. Samajdar, Y. C. Lin, T. Krishna, A. Raychowdhury
2024 IEEE International Symposium on Performance Analysis of Systems and Software [ISPASS24], Indianapolis, IN, USA (To appear in Main Program) -
H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations
Z. Wan*, C.-K. Liu*, M. Ibrahim, H. Yang, S. Spetalnick, T. Krishna, A. Raychowdhury
2024 IEEE/ACM Design Automation and Test in Europe [DATE24a], Valencia, Spain -
In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies
H. E. Barkam, S. Yun, P. R. Genssler, C.-K. Liu, Z. Zou, H. Amrouch, M. Imani
2024 IEEE Transactions on Circuits and Systems I: Regular Papers [TCAS-I24] -
FeReX: A Reconfigurable Design of Multi-bit Ferroelectric Compute-in-Memory for Nearest Neighbor Search
Z. Xu, C.-K. Liu, C. Li, R. Mao, J. Yang, T. K ̈ampfe, M. Imani, C. Li, C. Zhuo and X. Yin
2024 IEEE/ACM Design Automation and Test in Europe [DATE24b], Valencia, Spain -
SEE-MCAM: A Scalable Multi-bit FeFET Content Addressable Memory for Energy Efficient Associative Search
S. Shou, C.-K. Liu, S. Yun, Z. Wan, K. Ni, M. Imani, X. S. Hu, J. Yang, C. Zhuo, X. Yin
2023 IEEE/ACM International Conference on Computer-aided Design [ICCAD23], San Francisco, CA, USA -
Towards Cognitive AI System: A Survey and Prospective on Neuro-symbolic AI
Z. Wan, C.-K. Liu*, H. Yang*, C. Li*, H. You*, Y. Fu, C. Wan, T. Krishna, Y. C. Lin, A. Raychowdhury
2023 Systems for Next-Gen AI Paradigms Workshop, MLSys, Miami, Florida, USA -
HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable Highly-Scaled FeFET
H. E. Barkam, S. Yun, P. R. Genssler, Z. Zou, C.-K. Liu, H. Amrouch, M. Imani
2023 IEEE/ACM Design Automation and Test in Europe [DATE23], Antwerp, Belgium -
Cosime: Fefet based Associative Memory for In-memory Cosine Similarity Search
C.-K. Liu, H. Chen, M. Imani, K. Ni, A. Kazemi, A. F. Laguna, M. Niemier, X. S. Hu, Z. Liang, C. Zhuo, X. Yin
2022 IEEE/ACM International Conference on Computer-aided Design [ICCAD22], San Diego, CA, USA
Pre-prints
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Towards Efficient Hyperdimensional Computing Using Photonics
F. Fayza, C. Demirkiran, H. Chen, C.-K. Liu, A. Mohan, H. Errahmouni, S. Yun, M. Imani, D. Zhang, D. Bunandar, A. Joshi
2023 Arxiv
Service
- 2024 IEEE ISCAS Paper Reviewer
- 2023-2024 ACM JATS Paper Reviewer
- 2022-2023 IEEE JETCAS Paper Reviewer
Education
Ph.D. Student, Electrical and Computer Engineering
August 2023 - Present
B.Eng., Electronics Engineering
Aug 2019 - July 2023
Acknowledgements
This section is dedicated to expressing my deepest gratitude for the unreserved support and invaluable assistance I received from my colleagues and advisor throughout my Ph.D. journey, and will be updated from time to time. Without any of the help below, I would not have succeeded.
Big thank you to (in random order): Sam (now in NVIDIA, US) for guiding me on every aspect of mix-signal chip design, Young-Seok for compact layout guidance, Sigang (now Assit. Prof. in Korea) for technical assistance in digital chip design, Shota (now in Asahi Kasei Micro Devices Corp., Japan) for post-RC in analog chip design, Prof. Sathe for every aspect of the chip design and his PsyLab, Nealson for algorithm and digital chip design insights, Zishen for insightful architecture/research discussions, and of course Prof. Raychowdhury for everything. Lastly, thank you to all the funding agencies and TSMC for the support.